1.
S.balaji
– Dept.of Electronics&comm.engg.,k.karunanithi Inst.of Tech.,kannkannampal,coimbatore,tamil Nadu,india
2.
R.subhashini
– Dept.of Electronics&comm.engg.,k.karunanithi Inst.of Tech.,kannkannampal,coimbatore,tamil Nadu,india
Abstract
Design of area and power-efficient high-speed data path logic systems are one of the most substantial areas of research in VLSI system design, The Carry Select Adder (CSLA) provides a good compromise between cost and performance in carry propagation adder design. However, conventional CSLA is still area- consuming due to the dual ripple carry adder (RCA) structure. In this paper, modification is done at gate-level to reduce area and power consumption. The Modified Carry Select-Adder (MCSLA) is designed for 8-bit, 16-bit, 32-bit and 64-bit and then compared with conventional CSLA respective architectures, this work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by implementing in Xilinx FPGA. This CSLA structures are implemented in booth multiplier in order to increase the efficiency of the booth multiplier.
Keywords Application Specific Integrated Circuits (ASIC), area-efficient, CSLA, Low Power, Booth Multiplier
