1.
Neeta Choubey
– 1- Student, Oriental University, Indore, M.p
2.
H.r. Singh
– 2-principal, Oriental University, Indore, M.p.
Abstract
In parallel communication the cost as well
as complexity of the system increases due to
simultaneous transmission of data bits on multiple
wires. Serial communication alleviates this drawback
and emerges as effective candidate in many
applications for long distance communication as it
reduces the signal distortion because of its simple
structure. This paper focuses on the VHDL
implementation of UART with status register which
supports asynchronous serial communication. The
paper presents the architecture of UART which
indicates, during reception of data, parity error,
framing error, overrun error and break error using
status register. The whole design is functionally
verified using Xilinx ISE Simulator.
Keywords Universal Asynchronous Receiver Transmitter, Status Register, VHDL Implementation, ISE Simulator, Asynchronous Serial Communication
