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An Improved Architecture of 256 Bit CSLA for Reduced Area Applications

International Journal of Research in Signal Processing, Computing & Communication System Design

Volume 3 Issue 1

Published: 2017
Author(s) Name: E. Lavanya | Author(s) Affiliation: Assistant Professor, Sreenidhi Institute of Science & Technology, Hyderabad, Telangana, India.
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In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems and to reduce power consumption. In designing a adder carry generation is critical way to reduce number of transistors and to reduce power consumption. Carry Select Adder (CSLA) is one of the fastest adders used and there is further scope of reducing the area in CSLA structure. The proposed design is implemented by sharing the Common Boolean Logic term (CBL) to develop an area-efficient CSLA. one XOR and one inverter in each summation operation as well as one AND gate and one inverter in each carry-out operation and Through the multiplexer, the correct output is selected according to the logic states of the carry in signal. This paper proposes efficient SQRT CSLA (CBL CSLA) architecture in terms of area. 8-bit, 16-bit, 32-bit, 64-bit, 128 bit and 256 bit architectures of CBL based CSLA are designed and compared with regular CSLA and BEC based CSLA.

Keywords: Adder, Binary to Excess-1 Converter (BEC), Carry Select Adder (CSLA), Common Boolean Logic (CBL), Exclusive or (XOR).

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