Monday, 02 Oct, 2023




A Review on Design of Full Adder Circuit Using Shannon Modified Method

Rungta International Journal of Electrical and Electronics Engineering

Volume 2 Issue 1 & 2

Published: 2017
Author(s) Name: Balkrishna Choubey, Pankaj Kumar Mishra | Author(s) Affiliation: M.Tech Scholar, Dept. of Electronics and Telecommn., Swami Vivekanand Tech. Univ., Chhatisgarh.
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In this paper, an 8 bit high speed full adder is designed based on Shannons expansion. This adder is implemented by using CMOS process technology. The proposed adder provides compromise both cost and performance in carry propagation adder design. Since, in parallel adder the carry suffer from the propagation delay. As the adder block increases the propagation delay also increased. So to provide constant amount of propagation delay into the adder, look ahead carry adder design and to enhance the performance of this design Shannons expansion is used. It also reduced the computational time. So it will be faster than any other adder design.

Keywords: ALU, CMOS technology, Look ahead carry, Propagation delay, Shannons expansion.

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